1. Field of the Invention
The present invention relates to a fabrication method for a capacitor of a semiconductor memory device. More particularly, the present invention relates to a fabrication method for a stacked capacitor of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
As semiconductors enter the stage of the deep sub-micron manufacturing, the device dimensions continue to reduce; in another words, the allowable capacitor area becomes smaller in a DRAM device. The size of the software used in computers, on the other hand, is getting larger, the required memory capacity thus needs to be increased. With the demands of a continuous downsizing of the device dimension and an increase for the memory capacity, the conventional approach in fabricating a dynamic random access memory capacitor must be changed to accommodate the current trend of development of semiconductor devices.
Although a stacked capacitor is the major technique employed in the manufacturing for a conventional semiconductor capacitor, related research on stacked capacitor continues even the fabrication of semiconductors has entered the stage of deep sub-micro manufacturing.
Although a stacked capacitor, for example, the crown type, the fin type, the cylinder type or the spread type, can meet the demand of a highly integrated DRAM device, it is very difficult to use the stacked type capacitor for a 256 Mega or 1 Giga bit capacitor due to the limited design rule.
FIGS. 1A to 1E are schematic cross-sectional view showing the manufacturing of a double-sided stacked capacitor according to the prior art.
As shown in FIG. 1A, a substrate 100, comprising devices, is sequentially covered with a silicon oxide layer 102 and a silicon nitride layer 104. The silicon oxide layer 102 serves as an inter-layer dielectric (ILD), and the silicon nitride layer 104 is an etching stop layer during the formation of the double-sided crown structure of the capacitor.
Photolithography and etching are further conducted to define a contact opening 106 in the silicon oxide layer 102 and the silicon nitride layer 104. A doped polysilicon plug 107 is further formed in the contact opening 106.
Referring to FIG. 1B, an insulation layer 108 is then formed, covering the silicon nitride layer 104 and the polysilicon plug 107. Photolithography and etching are further conducted to define an opening 110 in the insulation layer 108, exposing the polysilicon plug 107 and a portion of the silicon nitride layer 104.
As shown in FIG. 1C, a conformal amorphous silicon layer 112 is formed on the substrate 100, covering the opening 110.
Referring to FIG. 1D, using the insulation layer 108 as a polishing stop layer, the amorphous silicon layer 112 covering the surface of the insulation layer 108 is removed, leaving the remaining amorphous silicon layer 112a in the opening 110.
Continuing to FIG. 1E, using the silicon nitride layer 104 as an etching stop layer, the insulation layer 108 covering the surface of the silicon nitride layer 104 is removed.
At this point, a capacitor with a crown structure is thus formed. A hemispherical grain polysilicon layer is then formed on the amorphous silicon layer 112a, followed by sequentially forming the dielectric layer of the capacitor and the upper electrode of the capacitor to complete the formation of a double-sided crown structured capacitor.
The capacitance of the capacitor formed according to the above prior art, however, can not meet the requirements of a 256M or 1G DRAM device.